An Extra-Regular, Compact, Low-Power Multiplier Design Using Triple-Expansion Schemes and Borrow Parallel Counter Circuits

This paper presents an extra regular, Two recently proposed designs, as the typical complexity-reduced, high-performance pipelined examples of the improved conventional architectures, multiplier architecture, using newly proposed multiplier are rectangular-styled wallace tree multiplier (RSWM triple-expansion schemes. It is based on a parallel for short)) [2] and limited switch dynamic logic counter circuitry, called borrow parallel counter, which multiplier (LSDL) [1]. utilizes 4-b 1-hot encoded signals and borrow bits, i.e. The RSWM design proposes a rectangular bits weighted 2, as building blocks for a compact, lowWallace-tree construction method. In this method, the power, large parallel multiplier implementation. partial products are divided into two groups and added Exampled by a 54 x 54-b (bit) multiplier, the scheme in the opposite direction. The partial products in the allows large multipliers to be generated from smaller first group are added downward, and the partial multipliers, tripling the size in each expansion (6 x 6-b products in the second group are added upward. This to18 x 18-b to 54 x 54-b). This significantly reduces the method eliminates the dead area that occurs in a general complexity of state of the art designs and achieves fullWallace tree design. It also optimized the carry self-testability without sacrificing high-performance. propagation between the two groups to realize high The preliminary circuit layouts and simulations have speed and a simple layout. Applying the method to a 54 demonstrated and confirmed the potential of the new x 54-bit multiplier, a 980 μm x 1000 μm (0.98 mm2) architecture. area size and a 600-MHz clock speed have been achieved using 0.18 μm CMOS technology.